Thread synchronization in a multi-thread, multi-flow network communications processor architecture
US8874878B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 28, 2012 |
| Grant date | Oct 28, 2014 |
| Priority date | — |
| Expiry date | May 8, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L47/2441
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Described embodiments provide a packet classifier for a network processor that generates tasks corresponding to each received packet. The packet classifier includes a scheduler to generate contexts corresponding to tasks received by the packet classifier from processing modules of the network processor. The packet classifier processes threads of instructions, each thread of instructions corresponding to a context received from the scheduler, and each thread associated with a data flow. A thread status table has N entries to track up to N active threads. Each status entry includes a valid status indicator, a sequence value, a thread indicator and a flow indicator. A sequence counter generates a sequence value for each data flow of each thread and is incremented when processing of a thread is started, and is decremented when a thread is completed. Instructions are processed in the order in which the threads were started for each data flow.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.