Recovery method for poor yield at integrated circuit die panelization
US8877523B2 · kind B2 · utility
2Cited by
4References
15Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 22, 2011 |
| Grant date | Nov 4, 2014 |
| Priority date | — |
| Expiry date | Feb 16, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15153
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for making a packaged integrated circuit is provided. The method includes making a first panel of encapsulated die. In some embodiments, if a threshold number of die are not positioned in proper positions in the first panel, the die are separated from the first panel. The separated die are subsequently encapsulated in other panels of encapsulated die. Conductive interconnects can be formed over the other panels. The other panels are then separated into integrated circuit packages.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.