Methods of forming a three-dimensional semiconductor device with a dual stress channel and the resulting device

US8877588B2 · kind B2 · utility

Assignee

• GlobalFoundries Inc. · KY

Inventors

• Daniel T. Pham · Clifton Park, US
• Werner Juengling · Boise, US
• William J. Taylor, Jr. · Clifton Park, US
• Robert J. Miller · Yorktown Heights, US

Key dates

• Filing date: Feb 11, 2013
• Grant date: Nov 4, 2014
• Expiry date: Mar 15, 2033

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/795

Abstract

One method includes forming first and second spaced-apart trenches extending at least partially into a semiconducting substrate defining a fin structure for the device, forming a stress-inducing material having a first type of stress in the first trench, forming a second stress-inducing material in the second trench, the second stress-inducing material having a second stress that is a different than the first type of stress, and forming a gate structure around a portion of the fin structure. One device includes first and second spaced-apart trenches in a semiconducting substrate defining at least a portion of a fin for the device, a stress-inducing material having a first type of stress in the first trench, a second stress-inducing material in the second trench, the second stress-inducing material having a second stress that is a different type than the first stress, and a gate structure around a portion of the fin structure.