Double-pattern gate formation processing with critical dimension control
US8877642B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 1, 2013 |
| Grant date | Nov 4, 2014 |
| Priority date | — |
| Expiry date | Feb 1, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/01
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Fabricating of one or more semiconductor devices with critical gate dimension control is facilitated by: providing a multilayer stack structure over a substrate; etching through the multilayer stack structure, with critical gate dimension control, to define multiple gate lines; providing a protective layer over the multiple gate lines; and patterning and cutting one or more gate lines of the multiple gate lines to facilitate defining multiple gate structures of the one or more semiconductor devices. Etching through the multilayer stack structure is facilitated by lithographically patterning the multilayer stack structure, and critical dimension feedback control is provided to at least one of the lithographically patterning or the etching through the multilayer stack structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.