Compact three dimensional vertical NAND and method of making thereof
US8878278B2 · kind B2 · utility
120Cited by
18References
24Claims
0Family size
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Key dates
| Filing date | Jan 30, 2013 |
| Grant date | Nov 4, 2014 |
| Priority date | — |
| Expiry date | May 11, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/35
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A NAND device has at least a 3×3 array of vertical NAND strings in which the control gate electrodes are continuous in the array and do not have an air gap or a dielectric filled trench in the array. The NAND device is formed by first forming a lower select gate level having separated lower select gates, then forming plural memory device levels containing a plurality of NAND string portions, and then forming an upper select gate level over the memory device levels having separated upper select gates.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.