Patent · US Active

Stacked fan-out semiconductor chip

US8878360B2 · kind B2 · utility

58Cited by
3References
10Claims
0Family size

Assignee

Inventors

Key dates

Filing dateJul 13, 2012
Grant dateNov 4, 2014
Priority date
Expiry dateJul 13, 2032

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH01L2924/19105
  • WIPO fieldSemiconductors
  • WIPO sectorElectrical engineering

Abstract

A stacked semiconductor device and method of manufacturing a stacked semiconductor device are described. The semiconductor device may include a reconstituted base layer having a plurality of embedded semiconductor chips. A first redistribution layer may contact the electrically conductive contacts of the embedded chips and extend beyond the boundary of one or more of the embedded chips, forming a fan-out area. Another chip may be stacked above the chips embedded in the base layer and be electrically connected to the embedded chips by a second redistribution layer. Additional layers of chips may be included in the semiconductor device.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.