Detecting logically non-significant operation based on opcode and operand and setting flag to decode address specified in subsequent instruction as different address
US8880852B2 · kind B2 · utility
3Cited by
4References
25Claims
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Key dates
| Filing date | Oct 26, 2011 |
| Grant date | Nov 4, 2014 |
| Priority date | — |
| Expiry date | Jan 3, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/34
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method, apparatus, and program product execute instructions of an instruction stream and detect logically non-significant operations in the instruction stream. Then, based on that detection, a target or source address of a subsequent instruction is adjusted. In some instances, doing so enables a greater number of addresses, e.g., registers, to be accessed in a given number of bit positions within an instruction format.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.