Low power scan flip-flop cell
US8880965B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 21, 2012 |
| Grant date | Nov 4, 2014 |
| Priority date | — |
| Expiry date | Feb 26, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318541
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A low power scan flip-flop cell includes a multiplexer, a master latch, a scan slave latch and a data slave latch. The master latch is connected to the multiplexer, and used for generating a first latch signal. The scan slave latch is connected to the master latch, and generates a scan output (SO) signal. The data slave latch is connected to the master latch, and generates a Q output depending on a scan enable (SE) input signal and the first latch signal. The Q output is maintained at a predetermined level during scan mode, which eliminates unnecessary switching of combinational logic connected to the scan flip-flop cell and thus reduces power consumption.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.