Redeposition control in MRAM fabrication process

US8883520B2 · kind B2 · utility

Assignee

• Avalanche Technology, Inc. · US

Inventors

• Kimihiro Satoh · Wilsonville, US
• Dong Ha Jung · Pleasanton, US
• Ebrahim Abedifard · Sunnyvale, US
• Parviz Keshtbod · Los Altos Hills, US
• Yiming Huai · Pleasanton, US
• Jing Zhang · Los Altos, US

Key dates

• Filing date: Jun 22, 2012
• Grant date: Nov 11, 2014
• Expiry date: Feb 9, 2033

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10N50/01

Abstract

Methods and structures are described to reduce metallic redeposition material in the memory cells, such as MTJ cells, during pillar etching. One embodiment forms metal studs on top of the landing pads in a dielectric layer that otherwise covers the exposed metal surfaces on the wafer. Another embodiment patterns the MTJ and bottom electrode separately. The bottom electrode mask then covers metal under the bottom electrode. Another embodiment divides the pillar etching process into two phases. The first phase etches down to the lower magnetic layer, then the sidewalls of the barrier layer are covered with a dielectric material which is then vertically etched. The second phase of the etching then patterns the remaining layers. Another embodiment uses a hard mask above the top electrode to etch the MTJ pillar until near the end point of the bottom electrode, deposits a dielectric, then vertically etches the remaining bottom electrode.