Semiconductor device with a passivation layer
US8884342B2 · kind B2 · utility
2Cited by
3References
30Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 29, 2012 |
| Grant date | Nov 11, 2014 |
| Priority date | — |
| Expiry date | Oct 20, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/112
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a semiconductor body with a first surface, a contact electrode arranged on the first surface, and a passivation layer on the first surface adjacent the contact electrode. The passivation layer includes a layer stack with an amorphous semi-insulating layer on the first surface, a first nitride layer on the amorphous semi-insulating layer, and a second nitride layer on the first nitride layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.