Semiconductor device and method of forming PIP with inner known good die interconnected with conductive bumps
US8884418B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 7, 2012 |
| Grant date | Nov 11, 2014 |
| Priority date | — |
| Expiry date | Oct 5, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3025
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A PiP semiconductor device has an inner known good semiconductor package. In the semiconductor package, a first via is formed in a temporary carrier. A first conductive layer is formed over the carrier and into the first via. The first conductive layer in the first via forms a conductive bump. A first semiconductor die is mounted to the first conductive layer. A first encapsulant is deposited over the first die and carrier. The semiconductor package is mounted to a substrate. A second semiconductor die is mounted to the first conductive layer opposite the first die. A second encapsulant is deposited over the second die and semiconductor package. A second via is formed in the second encapsulant to expose the conductive bump. A second conductive layer is formed over the second encapsulant and into the second via. The second conductive layer is electrically connected to the second die.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.