Substrate for semiconductor package and process for manufacturing
US8884443B2 · kind B2 · utility
5Cited by
65References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 16, 2013 |
| Grant date | Nov 11, 2014 |
| Priority date | — |
| Expiry date | May 16, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/10674
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package substrate includes a core portion, an upper circuit layer and a plurality of pillars. The pillars are disposed on and project upward from the upper circuit layer. Top surfaces of the pillars are substantially coplanar. The pillars provide an electrical interconnect to a semiconductor die. Solder joint reliability as between the substrate and the semiconductor die is improved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.