Semiconductor memory device and methods of operating the same
US8885419B2 · kind B2 · utility
2Cited by
1References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 13, 2012 |
| Grant date | Nov 11, 2014 |
| Priority date | — |
| Expiry date | Sep 20, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/26
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device comprises a memory cell array including a plurality of memory blocks each including a plurality of pages, wherein each of the plurality of pages includes at least one flag cell indicating whether data is in a corresponding page, and a peripheral circuit configured to read data of flag cells of a selected memory block in response to an erase request and to omit an erase operation on the selected memory block based on the data of the flag cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.