Finfet
US8889494B2 · kind B2 · utility
13Cited by
2References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 29, 2010 |
| Grant date | Nov 18, 2014 |
| Priority date | — |
| Expiry date | Dec 17, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/151
Abstract
A fin type transistor includes a dielectric layer on a substrate surface which serves to isolate the gate of the transistor from the substrate. The dielectric layer includes a non-selectively etched surface to produce top portions of fin structures which have reduce height variations across the wafer. The fin type transistor may also include a counter doped region at least below the S/D regions to reduce parasitic capacitance to improve its performance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.