Methods of forming stressed fin channel structures for FinFET semiconductor devices

US8889500B1 · kind B1 · utility

Assignee

• GlobalFoundries Inc. · KY

Inventors

• Vimal Kamineni · Mechanicville, US
• Derya Deniz · McKinney, US
• Abner Bello · Clifton Park, US
• Abhijeet Paul · Poway, US
• Robert J. Miller · Yorktown Heights, US
• William J. Taylor, Jr. · Clifton Park, US

Key dates

• Filing date: Aug 6, 2013
• Grant date: Nov 18, 2014
• Expiry date: Aug 6, 2033

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/017

Abstract

One illustrative method disclosed herein includes, among other things, forming a plurality of fin-formation trenches that define a fin, forming a first stressed layer within the trenches and above the fin and performing at least one etching process on the first stressed layer so as to define spaced-apart portions of the first stressed layer positioned at least partially within the trenches on opposite sides of the fin. The method also includes forming spaced-apart portions of a second stressed layer above the spaced-apart portions of the first layer, forming a third stressed layer above the fin between the spaced-apart portions of the second layer and, after forming the third layer, forming a conductive layer above the second and third layers.