Inventor · Clifton Park, NY, US

Abner Bello

13Patents
4h-index
22Co-inventors
52Inventor score

Filing activity: Jan 21, 2013 → Jan 15, 2019

Most-cited inventions

PatentTitleAreaCited byStatus
US8889500B1 Methods of forming stressed fin channel structures for FinFET semiconductor devices Electricity 20 Active
US8975142B2 FinFET channel stress using tungsten contacts in raised epitaxial source and drain Electricity 9 Active
US9093302B2 Methods of forming substantially self-aligned isolation regions on FinFET semiconductor devices and the resulting devices Electricity 7 Active
US9419137B1 Stress memorization film and oxide isolation in fins Electricity 6 Active
US9318388B2 Methods of forming substantially self-aligned isolation regions on FinFET semiconductor devices and the resulting devices Electricity 4 Active
US8975094B2 Test structure and method to facilitate development/optimization of process parameters Electricity 3 Active
US9911634B2 Self-contained metrology wafer carrier systems Electricity 1 Active
US10818528B2 Self-contained metrology wafer carrier systems Electricity 0 Active
US9117930B2 Methods of forming stressed fin channel structures for FinFET semiconductor devices Electricity 0 Active
US10343253B2 Methods and systems for chemical mechanical planarization endpoint detection using an alternating current reference signal Performing Operations; Transporting 0 Active
US10242895B2 Self-contained metrology wafer carrier systems Electricity 0 Active
US10931143B2 Rechargeable wafer carrier systems Electricity 0 Active
US9281249B2 Decoupling measurement of layer thicknesses of a plurality of layers of a circuit structure Physics 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.