Interconnection for memory electrodes
US8891280B2 · kind B2 · utility
37Cited by
6References
29Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 12, 2012 |
| Grant date | Nov 18, 2014 |
| Priority date | — |
| Expiry date | Jan 19, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/826
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Row and/or column electrode lines for a memory device are staggered such that gaps are formed between terminated lines. Vertical interconnection to central points along adjacent lines that are not terminated are made in the gap, and vertical interconnection through can additionally be made through the gap without contacting the lines of that level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.