Dynamic erase voltage step size selection for 3D non-volatile memory
US8891308B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 11, 2013 |
| Grant date | Nov 18, 2014 |
| Priority date | — |
| Expiry date | Sep 11, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques are provided for erasing memory cells in a 3D stacked non-volatile memory device in a way which avoids prolonging erase time as the erase speed deceases due to the accumulation of program-erase cycles. In particular, a step size for erase pulses can be set which is a function of the number of program-erase cycles, e.g., as indicated by a count of program-erase cycles, a loop count during programming which is a function of programming speed, or an initial program voltage which is a function of programming speed. Further, the erase operation can account for different erase speeds of memory cells in different word line layers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.