Error detection in high-speed asymmetric interfaces utilizing dedicated interface lines
US8892963B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 9, 2006 |
| Grant date | Nov 18, 2014 |
| Priority date | — |
| Expiry date | Nov 19, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2001/0094
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A system and method for detecting errors in high-speed asymmetric interfaces are described. Embodiments include transmitting digital data between a first system component and a second system component over a bidirectional interface, wherein the first component is significantly more intelligent than the second component. The first component receives a signature from the second component over a line of the interface concurrent with READ and WRITE operations over the interface. The latency associated with transmission of a signature from the second component to the first component is the time taken for the second component to compute a signature. The signature received is compared to a signature stored by the first component. Both signatures correspond to a particular READ or WRITE command. Based on the comparison, the first component determines whether the READ or WRITE operation was successful, and directs the second component as necessary.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.