Reduced resistance SiGe FinFET devices and method of forming same
US8895395B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 6, 2013 |
| Grant date | Nov 25, 2014 |
| Priority date | — |
| Expiry date | Jun 6, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/822
Abstract
A method for forming a fin field-effect transistor (FinFET) device, comprises forming a plurality of silicon fins on a substrate, depositing silicon germanium (SiGe) on the plurality of fins, forming a gate region by forming a dummy gate stack on a predetermined area of the fins including the SiGe, removing the SiGe from an area of the fins not covered by the dummy gate stack, forming a merged region in the area of the fins not covered by the dummy gate stack to form a source drain region, removing the dummy gate stack to expose the remaining SiGe in the gate region, mixing the SiGe with the silicon fins in the gate region to form SiGe fins, and depositing a gate dielectric and gate metal on the SiGe fins.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.