Tensile stressed doped amorphous silicon
US8895415B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 31, 2013 |
| Grant date | Nov 25, 2014 |
| Priority date | — |
| Expiry date | May 31, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/27
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The method and apparatus disclosed herein relate to preparing a stack structure for an electronic device on a semiconductor substrate. A particularly beneficial application of the method is in reduction of internal stress in a stack containing multiple layers of silicon. Typically, though not necessarily, the internal stress is a compressive stress, which often manifests as wafer bow. In some embodiments, the method reduces the internal stress of a work piece by depositing phosphorus doped silicon layers having low internal compressive stress or even tensile stress. The method and apparatus disclosed herein can be used to reduce compressive bow in stacks containing silicon.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.