Parallel data communications mechanism having reduced power continuously calibrated lines
US8898504B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 14, 2011 |
| Grant date | Nov 25, 2014 |
| Priority date | — |
| Expiry date | Oct 16, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/22
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A communications link includes multiple continuously calibrated parallel lines, wherein one or more lines are at least partially powered down while being continuously calibrated to reduce power consumption. In one aspect, at least N+1 lines (where N is the logical bus width) are periodically recalibrated, and at least one redundant line is powered down between calibrations. The redundant line could be either a true spare available for use as a replacement, or an extra line which carries functional data while other lines are being calibrated in turn. In another aspect, the logical bus width is variable, but does not exceed NMAX. When N<NMAX, lines not carrying functional data are partially powered down between calibrations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.