At-speed scan testing of clock divider logic in a clock module of an integrated circuit
US8898527B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 18, 2013 |
| Grant date | Nov 25, 2014 |
| Priority date | — |
| Expiry date | May 13, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318552
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An integrated circuit comprises scan test circuitry and additional circuitry subject to testing utilizing the scan test circuitry. The scan test circuitry comprises a scan chain having a plurality of scan cells. The integrated circuit further comprises a clock distribution network configured to provide clock signals to respective portions of the integrated circuit. The clock distribution network comprises at least one clock module comprising one or more clock dividers and associated clock divider logic, and the scan test circuitry is configured to permit testing of at least a portion of the clock divider logic. A given scan chain of the scan test circuitry may comprise first and second scan cells, with the first scan cell having a scan output coupled to a scan input of the second scan cell, and the second scan cell having a data input driven by an output of the clock divider logic.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.