Layout pattern correction for integrated circuits
US8898606B1 · kind B1 · utility
12Cited by
0References
20Claims
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Assignee
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Key dates
| Filing date | Nov 15, 2013 |
| Grant date | Nov 25, 2014 |
| Priority date | — |
| Expiry date | Nov 15, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/394
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A process and apparatus are provided for automated pattern-based semiconductor design layout correction. Embodiments include: determining a portion of a layout of an IC design, the portion comprising a first pattern of a plurality of routes connecting a plurality of design connections; determining one or more sets of the plurality of design connections based on the plurality of routes; and determining, by a processor, a second pattern of a plurality of routes connecting the plurality of design connections within the portion based on the one or more sets.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.