Semiconductor device and fabricating the same
US8901607B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 14, 2013 |
| Grant date | Dec 2, 2014 |
| Priority date | — |
| Expiry date | Jan 14, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D87/00
Abstract
The present disclosure provides a semiconductor device. The semiconductor device includes a substrate having a gate region, source and drain (S/D) regions separated by the gate region and a first fin structure in a gate region in the N-FET region. The first fin structure is formed by a first semiconductor material layer as a lower portion, a semiconductor oxide layer as a middle portion and a second semiconductor material layer as an upper portion. The semiconductor device also includes a second fin structure in S/D regions in the N-FET region. The second fin structure is formed by the first semiconductor material layer as a lower portion and the semiconductor oxide layer as a first middle portion, the first semiconductor material layer as a second middle portion beside the first middle and the second semiconductor material layer as an upper portion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.