Memory devices, circuits and, methods that apply different electrical conditions in access operations
US8902631B2 · kind B2 · utility
1Cited by
1References
20Claims
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Key dates
| Filing date | Aug 30, 2012 |
| Grant date | Dec 2, 2014 |
| Priority date | — |
| Expiry date | May 5, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0411
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device can include a plurality of physical blocks that each include a number of memory elements programmable between at least two different impedance states, the memory elements being subject to degradation in performance; and bias circuits configured to applying healing electrical conditions to at least one spare physical block that does not contain valid data; wherein the healing electrical conditions are different from write operation electrical conditions, and reverse degradation of the memory elements of the at least one spare physical block.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.