Flash memory with data retention bias
US8902669B2 · kind B2 · utility
14Cited by
11References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 8, 2012 |
| Grant date | Dec 2, 2014 |
| Priority date | — |
| Expiry date | Feb 27, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/349
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Charge leakage from a floating gate in a NAND flash memory die is reduced by applying a data retention bias to a word line extending over the floating gates. The data retention bias is applied to one or more selected word lines when the memory die is in idle mode, when no read, write, erase, or other commands are being executed in the memory die.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.