Inventor · Sunnyvale, CA, US

Chris Avila

91Patents
13h-index
56Co-inventors
79Inventor score

Filing activity: Jun 16, 2009 → Apr 10, 2017

Most-cited inventions

PatentTitleAreaCited byStatus
US8144512B2 Data transfer flows for on-chip folding Physics 115 Active
US8886877B1 In-situ block folding for nonvolatile memory Physics 44 Active
US8687421B2 Scrub techniques for use with dynamic read Physics 38 Active
US8307241B2 Data recovery in multi-level cell nonvolatile memory Physics 26 Active
US8132045B2 Program failure handling in nonvolatile memory Physics 23 Active
US8913431B1 Pseudo block operation mode in 3D NAND Physics 22 Active
US8180994B2 Optimized page programming order for non-volatile memory Physics 21 Active
US8902661B1 Block structure profiling in three dimensional memory Electricity 20 Active
US9092340B2 Method and system for achieving die parallelism through block interleaving Physics 17 Active
US9552171B2 Read scrub with adaptive counter management Physics 16 Active
US8423866B2 Non-volatile memory and method with post-write read and adaptive re-write to manage errors Physics 15 Active
US8902669B2 Flash memory with data retention bias Physics 14 Active
US8468294B2 Non-volatile memory with multi-gear control using on-chip folding of data Physics 13 Active
US9009568B2 Sensing parameter management in non-volatile memory storage system to compensate for broken word lines Physics 12 Active
US8902647B1 Write scheme for charge trapping memory Physics 12 Active
US8902658B1 Three-dimensional NAND memory with adaptive erase Physics 12 Active
US9384839B2 Write sequence providing write abort protection Physics 11 Active
US8830717B2 Optimized configurable NAND parameters Electricity 11 Active
US8966330B1 Bad block reconfiguration in nonvolatile memory Physics 11 Active
US9245637B2 Systems and methods for read disturb management in non-volatile memory Physics 11 Active
US9105349B2 Adaptive operation of three dimensional memory Physics 11 Active
US8964467B1 Systems and methods for partial page programming of multi level cells Physics 10 Active
US8971119B2 Select transistor tuning Physics 10 Active
US8909493B2 Compensation for sub-block erase Electricity 10 Active
US9015407B1 String dependent parameter setup Physics 10 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.