Semiconductor memory device and method of reading out the same
US8902674B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 19, 2012 |
| Grant date | Dec 2, 2014 |
| Priority date | — |
| Expiry date | Nov 18, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0483
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes a memory cell array configured to include memory cells, peripheral circuits configured to read out data stored in a selected memory cell in a read operation, and a controller configured to control the peripheral circuits so that the peripheral circuits sense a voltage level of the bit line when a first read voltage of the read voltages is supplied to the word line and the peripheral circuits sense voltage levels of the bit line when a second read voltage lower than the first read voltage by a specific level and a third read voltage higher than the first read voltage by the specific level are supplied to the word line in order to determine whether a threshold voltage of the selected memory cell falls within a set voltage distribution in the read operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.