Electrical leakage reduction in stacked integrated circuits having through-silicon-via (TSV) structures
US8907494B2 · kind B2 · utility
1Cited by
9References
15Claims
0Family size
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Key dates
| Filing date | Mar 14, 2013 |
| Grant date | Dec 9, 2014 |
| Priority date | — |
| Expiry date | Mar 14, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15311
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The formation of TSVs (through substrate vias) for 3D applications has proven to be defect dependent upon the type of starting semiconductor substrate employed. In addition to the initial formation of TSVs via Bosch processing, backside 3D wafer processing has also shown a defect dependency on substrate type. High yield of TSV formation can be achieved by utilizing a substrate that embodies bulk micro defects (BMD) at a density between 1e4/cc (particles per cubic centimeter) and 1e7/cc and having equivalent diameter less than 55 nm (nanometers).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.