Double verify method in multi-pass programming to suppress read noise
US8908441B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 15, 2013 |
| Grant date | Dec 9, 2014 |
| Priority date | — |
| Expiry date | Oct 15, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Memory cells which have read noise are identified during a programming pass and an amount of programming is increased for noisy memory cells compared to non-noisy cells. The read noise is indicated by a decrease in the threshold voltage of a cell when the cell is repeatedly read. In one approach, during the programming pass, a cell enters a temporary lockout state when it passes a first verify test and is subject to one or more additional verify tests. Data is stored to identify the cell as a noisy cell or a non-noisy cell based on the one or more additional verify tests. Or, the cells are subject to the one or more additional verify tests at the end of the programming pass. In a subsequent programming pass, the noisy cell is programmed using a stricter verify condition. Or, the noisy cell is kept in an erased state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.