Compensation for sub-block erase
US8909493B2 · kind B2 · utility
10Cited by
20References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 15, 2014 |
| Grant date | Dec 9, 2014 |
| Priority date | — |
| Expiry date | May 15, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B69/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A non-volatile memory system that has two or more sub-blocks in a block performs a check before accessing memory cells to see if the condition of a sub-block that is not being accessed could affect the memory cells being accessed. If such a sub-block is found then parameters used to access the cells may be modified according to a predetermined scheme.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.