Methods involving pattern matching to identify and resolve potential non-double-patterning-compliant patterns in double patterning applications
US8910090B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 27, 2013 |
| Grant date | Dec 9, 2014 |
| Priority date | — |
| Expiry date | Apr 13, 2033 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P90/02
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
One illustrative method disclosed herein involves producing an initial circuit layout, prior to decomposing the initial circuit layout, identifying at least one potential non-double-patterning-compliant (NDPC) pattern in the initial circuit layout, fixing the at least one potential non-double-patterning-compliant (NDPC) pattern so as to produce a double-patterning-compliant (DPT) pattern, producing a modified circuit layout by removing the potential non-double-patterning-compliant (NDPC) pattern and adding the double-patterning-compliant (DPT) pattern to the initial circuit layout, and performing design rule checking and double patterning compliance checking on the modified circuit layout.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.