Retargeting semiconductor device shapes for multiple patterning processes
US8910094B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 6, 2013 |
| Grant date | Dec 9, 2014 |
| Priority date | — |
| Expiry date | Feb 6, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2111/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method includes receiving a design layout file for an integrated circuit device in a computing apparatus. The design layout file specifies dimensions of a plurality of features. The design layout file is decomposed to a plurality of colored layout files, each colored layout file representing a particular reticle in a multiple patterning process. Each of the colored layout files is retargeted separately in the computing apparatus to generate a plurality of retargeted colored layout files. Retargeting each of the colored layout files includes increasing dimensions of a first plurality of features based on spacings between the first plurality of features and adjacent features. The retargeted layout files are combined to generate a combined layout file. Features in the combined layout file are retargeted in the computing apparatus to increase dimensions of a second plurality of features based on spacings between the second plurality of features and adjacent features.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.