Norman Chen
26Patents
4h-index
38Co-inventors
63Inventor score
Filing activity: Dec 3, 2003 → Dec 15, 2022
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7432042B2 | Immersion lithography process and mask layer structure applied in the same | Physics | 34 | Expired |
| US9026977B2 | Power rail layout for dense standard cell library | Physics | 14 | Active |
| US10459352B2 | Mask cleaning | Physics | 6 | Active |
| US8782571B2 | Multiple patterning process for forming trenches or holes using stitched assist features | Physics | 5 | Active |
| US8010915B2 | Grid-based fragmentation for optical proximity correction in photolithography mask applications | Physics | 4 | Active |
| US7642101B2 | Semiconductor device having in-chip critical dimension and focus patterns | Electricity | 3 | Active |
| US10386715B2 | Methodology for post-integration awareness in optical proximity correction | Physics | 2 | Active |
| US8612904B1 | Use of polarization and composite illumination source for advanced optical lithography | Physics | 2 | Active |
| US9443055B2 | Methods for retargeting circuit design layouts and for fabricating semiconductor devices using retargeted layouts | Emerging Cross-Sectional Technologies | 1 | Active |
| US7838205B2 | Utilization of electric field with isotropic development in photolithography | Physics | 1 | Active |
| US7387969B2 | Top patterned hardmask and method for patterning | Electricity | 1 | Expired |
| US7776494B2 | Lithographic mask and methods for fabricating a semiconductor device | Physics | 1 | Active |
| US9171735B2 | Method for fabricating a semiconductor integrated circuit with a litho-etch, litho-etch process for etching trenches | Physics | 1 | Active |
| US8993224B2 | Multiple patterning process for forming trenches or holes using stitched assist features | Physics | 1 | Active |
| US8910094B2 | Retargeting semiconductor device shapes for multiple patterning processes | Physics | 1 | Active |
| US9886543B2 | Method providing for asymmetric pupil configuration for an extreme ultraviolet lithography process | Physics | 0 | Active |
| US9064086B2 | Retargeting semiconductor device shapes for multiple patterning processes | Physics | 0 | Active |
| US11921434B2 | Mask cleaning | Physics | 0 | Active |
| US9484300B2 | Device resulting from printing minimum width semiconductor features at non-minimum pitch | Emerging Cross-Sectional Technologies | 0 | Active |
| US10401837B2 | Generating risk inventory and common process window for adjustment of manufacturing tool | Emerging Cross-Sectional Technologies | 0 | Active |
| US8472005B2 | Methodology for implementing enhanced optical lithography for hole patterning in semiconductor fabrication | Physics | 0 | Active |
| US9091923B2 | Contrast enhancing exposure system and method for use in semiconductor fabrication | Physics | 0 | Active |
| US11256179B2 | Mask cleaning | Physics | 0 | Active |
| US11740563B2 | Mask cleaning | Physics | 0 | Active |
| US9366969B2 | Methodology for implementing enhanced optical lithography for hole patterning in semiconductor fabrication | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.