Thread synchronization in a multi-thread network communications processor architecture
US8910171B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 21, 2010 |
| Grant date | Dec 9, 2014 |
| Priority date | — |
| Expiry date | Sep 18, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L47/522
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Described embodiments provide a packet classifier for a network processor that generates tasks corresponding to each received packet. The packet classifier includes a scheduler to generate contexts corresponding to tasks received by the packet classifier from a plurality of processing modules of the network processor. A multi-thread instruction engine processes threads of instructions, each thread of instructions corresponding to a context received from the scheduler. A thread status manager maintains a thread status table having N entries to track up to N active threads. Each status entry includes a valid status indicator, a sequence value, and a thread indicator. A sequence counter generates a sequence value for each thread and is incremented when processing of a thread is started, and is decremented when a thread is completed, by the multi-thread instruction engine. Instructions are processed by the multi-thread instruction engine in the order in which the threads were started.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.