Patent · US Active

Stacked die assembly having reduced stress electrical interconnects

US8912661B2 · kind B2 · utility

2Cited by
117References
24Claims
0Family size

Assignee

Inventors

Key dates

Filing dateNov 4, 2010
Grant dateDec 16, 2014
Priority date—
Expiry dateNov 4, 2030

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH01L2924/351
  • WIPO fieldSemiconductors
  • WIPO sectorElectrical engineering

Abstract

Methods are disclosed for improving electrical interconnection in stacked die assemblies, and stacked die assemblies are disclosed having structural features formed by the methods. The resulting stacked die assemblies are characterized by having reduced electrical interconnect failure.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.