Wafer-level package and method of manufacturing the same
US8912662B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 30, 2013 |
| Grant date | Dec 16, 2014 |
| Priority date | — |
| Expiry date | Feb 14, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/18161
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A wafer-level package and a method of manufacturing the same. The wafer-level package includes a first semiconductor chip on an upper side of which an active surface facing downward is disposed, a redistribution formed on the active surface of the first semiconductor chip, a second semiconductor chip disposed on the redistribution using a flip-chip bonding (FCP) technique, a copper (Cu) post and a first solder ball sequentially disposed on the redistribution, a molding member formed on the active surface of the first semiconductor chip to expose a bottom surface of the first solder ball and an inactive surface of the second semiconductor chip, and a second solder ball disposed on the first solder ball and electrically connected to an external apparatus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.