Patent · US Active

Multi-port DRAM architecture for accessing different memory partitions

US8914589B2 · kind B2 · utility

9Cited by

13References

33Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Peter Gregorius · Munich, DE
Thomas Hein · Hersbruck, DE
Martin Maier · Asperg, DE
Hermann Ruckerbauer · Radolfzell, DE
Thilo Schaffroth · Weingarten, DE
Ralf Schedel · Rödental, DE
Wolfgang Anton Spirkl · Germering, DE
Johannes Stecker · Birkenfeld, DE

Key dates

Filing date	Sep 22, 2008
Grant date	Dec 16, 2014
Priority date	—
Expiry date	Aug 31, 2031

Classification

Technology area (CPC Y)Emerging Cross-Sectional Technologies
CPC primaryY02D10/00
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Embodiments of the invention provide a memory device that may be accessed by a plurality of controllers or processor cores via respective ports of the memory device. Each controller may be coupled to a respective port of the memory device via a data bus. Each port of the memory device may be associated a predefined section of memory, thereby giving each controller access to a distinct section of memory without interference from other controllers. A common command/address bus may couple the plurality of controllers to the memory device. Each controller may assert an active signal on a memory access control bus to gain access to the command/address bus to initiate a memory access.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.