Embedded wafer level package for 3D and package-on-package applications, and method of manufacture
US8916481B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 6, 2011 |
| Grant date | Dec 23, 2014 |
| Priority date | — |
| Expiry date | Feb 11, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K1/186
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process for manufacturing a 3D or PoP semiconductor package includes forming a redistribution layer on a reconstituted wafer, then laser drilling a plurality of apertures in the reconstituted wafer, extending from an outer surface of the reconstituted wafer to intersect electrical traces in the first redistribution layer. A solder ball is then positioned adjacent to an opening of each of the apertures. The solder balls are melted and allowed to fill the apertures, making contact with the respective electrical traces and forming a plurality of solder columns. The outer surface of the reconstituted wafer is then planarized, and a second redistribution layer is formed on the planarized surface. The solder columns serve as through-vias, electrically coupling the first and second redistribution layers on opposite sides of the reconstituted wafer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.