Implementing instruction set architectures with non-contiguous register file specifiers
US8918623B2 · kind B2 · utility
22Cited by
11References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 21, 2012 |
| Grant date | Dec 23, 2014 |
| Priority date | — |
| Expiry date | Jan 25, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30181
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
There are provided methods and computer program products for implementing instruction set architectures with non-contiguous register file specifiers. A method for processing instruction code includes processing an instruction of an instruction set using a non-contiguous register specifier of a non-contiguous register specification. The instruction includes the non-contiguous register specifier.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.