Mesochronous signaling system with clock-stopped low power mode
US8918669B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 9, 2009 |
| Grant date | Dec 23, 2014 |
| Priority date | — |
| Expiry date | Aug 14, 2031 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a low-power signaling system, an integrated circuit device includes an open loop-clock distribution circuit and a transmit circuit that cooperate to enable high-speed transmission of information-bearing symbols unaccompanied by source-synchronous timing references. The open-loop clock distribution circuit generates a transmit clock signal in response to an externally-supplied clock signal, and the transmit circuit outputs a sequence of symbols onto an external signal line in response to transitions of the transmit clock signal. Each of the symbols is valid at the output of the transmit circuit for a symbol time and a phase offset between the transmit clock signal and the externally-supplied clock signal is permitted to drift by at least the symbol time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.