Patent · US Active

Integrated circuit schematics having imbedded scaling information for generating a design instance

US8918749B2 · kind B2 · utility

2Cited by

5References

6Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Michael Kugel · Eppelheim, DE
Stefan Payer · Stuttgart, DE
Raphael Polig · Dietikon, CH
Tobias Werner · Holzgerlingen, DE

Key dates

Filing date	Nov 6, 2013
Grant date	Dec 23, 2014
Priority date	—
Expiry date	Nov 6, 2033

Classification

Technology area (CPC G)Physics
CPC primaryG06F30/398
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A non-transitory computer-readable memory including first data representative of a topology of a circuit including a first circuit element and a second circuit element, and second data representative of a scaling rule for the first circuit element as a function of the second circuit element. A data processing method comprising retrieving first data representative of a topology of a circuit comprising a first circuit element and a second circuit element from a memory, retrieving second data representative of a scaling rule for the first circuit element as a function of the second circuit element from the memory, receiving a user input representative of a scaling factor, generating third data representative of an instance of the second circuit element using the scaling factor, and generating data representative of an instance of the first circuit element using the scaling factor, the scaling rule and the third data.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.