Isolation scheme for bipolar transistors in BiCMOS technology
US8921195B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 26, 2012 |
| Grant date | Dec 30, 2014 |
| Priority date | — |
| Expiry date | Dec 13, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D10/891
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods for fabricating a device structure, as well as device structures and design structures for a bipolar junction transistor. The device structure includes a collector region in a substrate, a plurality of isolation structures extending into the substrate and comprised of an electrical insulator, and an isolation region in the substrate. The isolation structures have a length and are arranged with a pitch transverse to the length such that each adjacent pair of the isolation structures is separated by a respective section of the substrate. The isolation region is laterally separated from at least one of the isolation structures by a first portion of the collector region. The isolation region laterally separates a second portion of the collector region from the first portion of the collector region. The device structure further includes an intrinsic base on the second portion of the collector region and an emitter on the intrinsic base. The emitter has a length transversely oriented relative to the length of the isolation structures.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.