Stressed channel FET with source/drain buffers

US8921939B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Jeffrey B. Johnson · Hague, US
• Ramachandran Muralidhar · Austin, US
• Philip J. Oldiges · Lagrangeville, US
• Viorel Ontalus · Danbury, US
• Kai Xiu · White Plains, US

Key dates

• Filing date: Jan 28, 2013
• Grant date: Dec 30, 2014
• Expiry date: Jan 28, 2033

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/822

Abstract

A stressed channel field effect transistor (FET) includes a substrate; a gate stack located on the substrate; a channel region located in the substrate under the gate stack; source/drain stressor material located in cavities in the substrate on either side of the channel region; and vertical source/drain buffers located in the cavities in the substrate between the source/drain stressor material and the substrate, wherein the source/drain stressor material abuts the channel region above the source/drain buffers.