Die up fully molded fan-out wafer level packaging
US8922021B2 · kind B2 · utility
5Cited by
13References
28Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Sep 12, 2013 |
| Grant date | Dec 30, 2014 |
| Priority date | — |
| Expiry date | Sep 12, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing a semiconductor chip comprising placing a plurality of die units each having an active front surface and a back surface facing front surface up on an encapsulant layer, encapsulating the plurality of die units on the active surface of the encapsulant layer with an encapsulant covering a front surface and four side surfaces of each of the plurality of die units, and exposing, through the encapsulation on the front surface, conductive interconnects electrically connecting a die bond pad to a redistribution layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.