3D IC testing apparatus

US8922230B2 · kind B2 · utility

Assignee

• TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD. · TW

Inventors

• Mill-Jer Wang · Hsinchu, TW
• Chih-Chia Chen · Hsinchu, TW
• Hung-Chih Lin · Baoshan, TW
• Ching-Nen Peng · Hsinchu, TW
• Hao Chen

Key dates

• Filing date: May 11, 2011
• Grant date: Dec 30, 2014
• Expiry date: Feb 21, 2033

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y02P80/30
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

A three dimensional (3D) integrated circuit (IC) testing apparatus includes a plurality of connection devices. When a device under test (DUT) such as an interposer or a 3D IC formed by a plurality of 3D dies operates in a testing mode, the 3D IC testing apparatus is coupled to the DUT via a variety of interface channels such as probes. The connection devices and a variety of through silicon vias (TSVs) in the DUT form a TSV chain so that an electrical characteristic test of the variety of TSVs can be tested all at once.