Semiconductor integrated circuit with testing and repairing via
US8922237B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 5, 2012 |
| Grant date | Dec 30, 2014 |
| Priority date | — |
| Expiry date | Apr 3, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A semiconductor integrated circuit includes a plurality of semiconductor chips coupled to one another through vias, wherein a lowermost semiconductor chip of the plurality of semiconductor chips is configured to generate a first test pulse signal and transmit the first test pulse signal through the via, an uppermost semiconductor chip of the plurality of semiconductor chips is configured to generate a second test pulse signal while substantially maintaining a time difference with the first test pulse signal, and to transmit the second test pulse signal through the via, and the plurality of semiconductor chips are configured to generate test result signals for determining whether the vias are defective in response to the first test pulse signal and the second test pulse signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.