Automated design layout pattern correction based on context-aware patterns
US8924896B2 · kind B2 · utility
4Cited by
18References
16Claims
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Key dates
| Filing date | Jan 31, 2013 |
| Grant date | Dec 30, 2014 |
| Priority date | — |
| Expiry date | Jan 31, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/398
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A process and apparatus are provided for automated pattern-based semiconductor design layout correction. Embodiments include scanning a drawn semiconductor design layout to determine a difficult-to-manufacture pattern within the drawn semiconductor design layout based on a match with a pre-characterized difficult-to-manufacture pattern, determining a corrected pattern based on a pre-determined correlation between the corrected pattern and the pre-characterized difficult-to-manufacture pattern, and replacing the difficult-to-manufacture pattern with the corrected pattern within the drawn semiconductor design layout.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.