Method for bonding of chips on wafers
US8927335B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 3, 2010 |
| Grant date | Jan 6, 2015 |
| Priority date | — |
| Expiry date | Sep 15, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15738
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Method for bonding of a plurality of chips onto a base wafer which contains chips on the front, the chips being stacked in at least one layer on the back of the base wafer and electrically conductive connections are established between the vertically adjacent chips, with the following steps: a) fixing of the front of the base wafer on a carrier, b) placing at least one layer of chips in defined positions on the back of the base wafer, and c) heat treatment of the chips on the base wafer fixed on the carrier, characterized in that prior to step c) at least partial separation of the chips of the base wafer into separated chip stack sections of the base after takes place.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.